1. Technical Field
The inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly to, a semiconductor device having a vertical gate and a method of manufacturing the same.
2. Related Art
As the integration degree of semiconductor devices is increased, channel lengths of transistors are gradually reduced. The reduction of the channel lengths of the transistors causes a short channel effect such as drain induced barrier lowering (DIBL), a hot carrier effect, and punch-through. So as to solve this problem, various methods such as a method of reducing a depth of a junction region or a method of relatively increasing a channel length by forming a recess in a channel region of a transistor have been suggested.
However, as the integration density of the semiconductor memory devices, in particular, dynamic random access memories (DRAMs) approach Giga bit, transistors having a smaller size is demanded. That is, transistors of DRAMs having a Giga-bit grade require a device area of below 8F2 (F: minimum feature size), further a device area of about 4F2. Accordingly, it is difficult to satisfy the desired device area in a current planar transistor structure in which a gate electrode is formed on a semiconductor substrate and junction regions are formed at both sides of the gate electrode even when scaling the channel length. So as to solve this problem, a vertical channel transistor structure has been suggested.
In the vertical channel transistor structure, as a linewidth of a device is reduced, a body floating effect in which a body region is electrically isolated from a silicon substrate by a source/drain junction regions located below a vertical gate is caused. When the body floating effect is caused, a threshold voltage of the transistor is varied by hole charges accumulated in the body.